Siemens Tessent & Crypto Quantique

Securing DFT for the Silicon Lifecycle Era

Crypto Quantique partners with Siemens Tessent to embed production-ready security directly into Design-for-Test (DFT) and Silicon Lifecycle Management (SLM) flows.

Together, we enable chiplet and advanced SoC designs to remain secure from wafer probe through in-field operation — without compromising performance, area, or time-to-market.

The Challenge

Modern silicon requires lifecycle visibility — predictive maintenance, OTA validation, in-field diagnostics, supply chain traceability.

However, traditional DFT and IJTAG infrastructures were not built for post-manufacturing security. After shipment, test ports either remain exposed (creating attack surfaces) or are disabled (blocking SLM and telemetry).

At the same time, design teams face:

  • Increasing regulatory pressure (e.g. EU CRA)

  • Tight PPA constraints

  • Long integration cycles for new security IP

  • Risk associated with onboarding new vendors

Security must integrate seamlessly into existing Tessent flows — without slowing development.

The Solution

Crypto Quantique provides low gate-count, silicon-proven security IP that integrates directly into Siemens Tessent DFT and IJTAG infrastructures.

Together we enable:

  • Cryptographic identity anchored in hardware

  • Authenticated and encrypted access to IJTAG post-manufacturing

  • Secure provisioning from wafer to field

  • Verified in-system test and trusted telemetry

  • Lifecycle monitoring without exposing test logic

Unlike bolt-on fixes, protections are embedded and verified inside Tessent flows — eliminating custom security builds or cross-team coordination.

“Crypto Quantique allowed us to integrate production-ready security IP into our solution in weeks
rather than months, with minimal overhead and full confidence in the result.”

— Lee Harrison, Siemens Tessent

Why It Matters

As chiplet architectures scale and supply chains fragment, DFT becomes a critical security boundary.

By embedding identity, access control, and cryptographic enforcement directly into test infrastructures, Crypto Quantique and Siemens Tessent ensure lifecycle visibility is secure, practical, and compliant by default.

Learn More

Explore Siemens Tessent’s Silicon Lifecycle Management solutions
or Contact us to discuss securing DFT and chiplet architectures in your next-generation design.

Visit Siemens EDA Tessent

Contact us