Crypto Quantique is a rapidly growing scale-up pioneering hardware security for the Internet of Things. Building on advanced research in cryptography and semiconductor design, we are developing secure Root of Trust systems and post-quantum cryptographic solutions that bring trust and resilience to connected devices. Operating at the convergence of hardware security, cryptography, and embedded systems, you’ll work on technologies that will define the next generation of secure IoT infrastructure.
As a Digital Design Engineer – Hardware Security for IoT, you’ll play a key role in designing and implementing secure digital architectures for ASIC and FPGA platforms. You’ll work on optimizing cryptographic implementations for constrained environments, developing modules for algorithms such as AES and SHA, and ensuring robustness against side-channel attacks. This role offers deep technical engagement across the full digital design lifecycle—from architecture and RTL design to synthesis, verification, and timing analysis—while collaborating closely with hardware, software, and verification teams.
Responsibilities
- Design, develop, and verify digital hardware modules for high-security applications, focusing on resource optimization (area, power, and memory).
- Implement a range of cryptographic algorithms and security primitives efficiently in hardware (e.g., AES, SHA, True Random Number Generators).
- Apply secure digital design techniques, including side-channel countermeasures, and optimize for performance and protection against side-channel attacks.
- Contribute to the full digital design lifecycle: specification, architecture, RTL coding (Verilog/VHDL), synthesis, static timing analysis (STA), formal verification, and testing.
- Collaborate closely with ASIC and embedded software teams to integrate secure digital components.
- Use software skills (e.g., Python scripting) to support hardware design, analysis, verification, and automated testing flows.
Experience
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5+ years of industrial experience in digital design with a proven track record of delivering high-quality designs, or 2+ years of industry experience combined with a Ph.D. in cryptography or related topics.
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Strong theoretical and practical understanding of cryptographic algorithms (symmetric and asymmetric) and their hardware architectures.
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Proven experience in digital implementation and optimization for low-power and constrained hardware environments.
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Proficiency with industry-standard digital design languages (Verilog/VHDL), testbench creation for verification, and timing analysis.
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Hands-on experience developing robust designs for ASIC and FPGA targets.
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Excellent analytical and problem-solving skills, with the ability to work effectively in a fast-paced, collaborative team environment.
Requirements
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Bachelor’s or Master’s degree in Electrical or Computer Engineering (Ph.D. desirable).
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Deep understanding of digital design principles and secure hardware architectures.
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Competence in scripting and automation (Python preferred) for analysis, testing, and design support.
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Strong communication skills and adaptability to evolving design specifications and team requirements.
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Enthusiasm for working in an innovative, fast-moving scale-up where ownership and creativity are encouraged.
Bonus Qualifications & Experience
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Familiarity with Post-Quantum Cryptography (PQC) algorithms and their hardware implementation challenges.
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Experience with Root of Trust, Secure Element, or Hardware Security Module (HSM) architectures, and related cryptographic mechanisms such as Secure Boot.
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Exposure to RISC-V processor cores, microarchitecture, and standards.
Keywords: Verilog, VHDL, RTL, ASIC, FPGA, Root of Trust, Post-Quantum Cryptography, AES, SHA, TRNG, STA, HSM, Hardware Security
